Designed and implemented a 4x4 sequential multiplier circuit using VHDL.
Overview
This project implemented a 4x4 sequential multiplier circuit using VHDL. The circuit multiplies two 4-bit binary numbers, producing an 8-bit result. Key components include shift registers, a counter, and a full adder for iterative computation.
Design
The multiplier design used two 4-bit shift registers to store inputs, a 9-bit custom shift register for the intermediate results, and a 4-bit counter to control iteration. The system controller managed data flow and computation timing, while the full adder computed partial products iteratively.
Simulation
Verified functionality using ISim simulation software. The circuit produced accurate results for a range of test cases, confirming the correct implementation of sequential multiplication.